Semiconductor memory devices may be classified into volatile memory devices that lose information stored therein when not powered, and non-volatile memory devices that retain stored information even when not powered. In recent years, of the non-volatile memory devices, flash memories have been increasingly used.
Example FIGS. 1A to 1C illustrate the structure of a flash memory cell. As illustrated in example FIG. 1A, the flash memory cell array has a string shape in which a plurality of memory cell units 10 are connected to each other in a row. Each memory cell unit 10 is connected to a word line and connected through a select transistor to a bit line. The bit line is connected to a drain through a contact hole formed on an insulating film.
As illustrated in example FIG. 1B, the flash memory cell unit 10 may include active area 11 where a channel is formed when a voltage is applied, floating gate 12 to store charges injected through tunneling, drain contact 13 serving as a bit line, and control gate 14 serving as a word line when the memory cell is erased or read.
As illustrated in example FIG. 1C, the flash memory cell unit includes tunneling oxide layer 21, floating gate 22, oxide/nitride/oxide (ONO) layer 23, control gate 24, spacer 25 having a double-layered structure composed of oxide and nitride layers, and drain contact 26.
The trend towards miniaturization and integration of semiconductor devices has brought about a decrease in word line pitch of flash memories and a decrease in the distance between gate electrode spacers.
Accordingly, as illustrated in example FIG. 2, the decrease in the space between gate electrodes disadvantageously causes voids in the process of depositing interlayer dielectric films. In addition, in an M1C (metal 1 contact) process, voids occur, which causes bridges between cells in contact metal gap-fill processes and thus malfunction of the cells.
Accordingly, example FIGS. 3A to 3C illustrate a method for fabricating a semiconductor device to prevent formation of voids on an interlayer dielectric film.
As illustrated in example FIG. 3A, an ONO layer including first oxide film 45, nitride film 46 and second oxide film 47 are sequentially deposited on and/or over the entire surface of a substrate including a gate electrode provided with tunneling oxide film 41, floating gate 42, oxide/nitride/oxide (ONO) layer 43 and control gate 44.
As illustrated in example FIG. 3B, through a first etching process, first oxide film 45, nitride film 46 and second oxide film 47 are partially etched to form a spacer. The first etching is carried out via anisotropic dry etching. As a result, area A′ where a drain contact is to be formed is provided in space A between adjacent gate electrodes.
As illustrated in example FIG. 3C, a secondary etching process is then performed until second oxide film 47 present on and/or over the outermost layer of the spacer is completely removed. The secondary etching is carried out via anisotropic wet etching using an etching material having a high etch selectivity for the oxide film in relation to the nitride film. As second oxide film 47 is completely removed, space B between the gate electrodes is then increased. Accordingly, in subsequent processes, upon gap-filling of interlayer dielectric films, no void is formed and gap-fill margin is thus improved.
However, during the secondary etching, as the wet etching proceeds, first oxide film 45 arranged under nitride film 46 is also etched, thus disadvantageously causing undercut B′ to be formed. Furthermore, in metal contact line (M1C) processes, contact metal materials flow in the undercut B′, thus disadvantageously resulting in bridges between the devices.